TSMC customers are more focused on making their hardware energy efficient than any other metric of improvement, Kevin Zhang, deputy co-chief operations officer and SVP at TSMC, said during the company’s Technology Symposium in Amsterdam on May 28.

Speaking during a press briefing, Zhang said that across the board – from Edge to mobile, IoT, HPC, or in the data center – customers want “more energy-efficient compute,” and that has now become the most important attribute for next-generation technology.

Turning to TSMC’s roadmap, Zhang noted that the company is currently targeting a 30 percent efficiency improvement per generation, and is “on track to achieve that goal,” even with 1MW+ chips expected before the end of the decade.

“Where you have 1000W chips, and the question is how do you resolve those thermal challenges, I see a clear solution path based on the innovation work we’re doing today that will allow us to solve the problem down the road,” he said.

Although he declined to go into further detail, Zhang said that a lot of R&D was currently being undertaken by the company with regard to “innovative materials” that can better address thermal challenges. Advancements in integrated photonics solutions can also help to provide more significant power benefits, he noted.

His comments come a month after TSMC unveiled three new fabrication processes: A12 and A13, 1.2nm and 1.3nm technologies, and N2U, an extension of the chipmaker’s N2 (2nm) family. A12, which will target AI and HPC applications, is set to feature Super Power Rail technology to provide backside power delivery, “significantly improving power delivery efficiency.”

According to internal forecasts from TSMC, by 2030, the global semiconductor market will hit $1.5 trillion, with 55 percent of all chips being produced by the end of the decade supporting AI and HPC applications.